XC3SD3400A-4FGG676C Datasheet, PDF (22/101 Pages) Xilinx, Inc – Spartan-3A DSP FPGA Family Data Sheet

Spartan-3A DSP FPGA Family: DC and Switching Characteristics
Input Setup and Hold Times
Table 19: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
DELAY_
VALUE
Device
Speed
-5 -4
Min Min
Units
Setup Times
T_IOPICK Time from the setup of data at the Input LVCMOS25⁽²⁾ IFD_DELAY_VALUE=0 XC3SD1800A 1.65 1.81 ns
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). No Input
XC3SD3400A 1.51 1.88 ns
Delay is programmed.
T_IOPICKD Time from the setup of data at the Input LVCMOS25⁽²⁾
1
XC3SD1800A 2.09 2.24 ns
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). The
2
2.67 2.83 ns
Input Delay is programmed.
3
3.25 3.64 ns
4
3.75 4.20 ns
5
3.69 4.16 ns
6
4.47 5.09 ns
7
5.27 6.02 ns
8
5.79 6.63 ns
1
XC3SD3400A 2.07 2.44 ns
2
2.57 3.02 ns
3
3.44 3.81 ns
4
4.01 4.39 ns
5
3.89 4.26 ns
6
4.43 5.08 ns
7
5.20 5.95 ns
8
5.70 6.55 ns
Hold Times
T_IOICKP Time from the active transition at the
LVCMOS25⁽³⁾
0
XC3SD1800A –0.63 –0.52 ns
ICLK input of the Input Flip-Flop (IFF) to
the point where data must be held at the
XC3SD3400A –0.56 –0.56 ns
Input pin. No Input Delay is programmed.
DS610 (v3.0) October 4, 2010
www.xilinx.com
Product Specification
22