SM320F2808-EP Datasheet, PDF (98/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
www.ti.com
Table 6-23. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
Micro Edge Positioning (MEP) step size⁽¹⁾
MIN
TYP MAX UNIT
150 310 ps
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the Texas
Instruments software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP
steps per SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-24 shows the eCAP timing requirement and Table 6-25 shows the eCAP switching characteristics.
Table 6-24. Enhanced Capture (eCAP) Timing Requirement⁽¹⁾
TEST CONDITIONS
t_w(CAP)
Capture input pulse width
Asynchronous
Synchronous
With input qualifier
(1) For an explanation of the input qualifier parameters, see Table 6-13.
MIN
2t_c(SCO)
2t_c(SCO)
1t_c(SCO) + t_w(IQSW)
Table 6-25. eCAP Switching Characteristics
MAX
UNIT
cycles
cycles
cycles
t_w(APWM)
PARAMETER
Pulse duration, APWMx output high/low
TEST CONDITIONS
MIN
MAX UNIT
20
ns
Table 6-26 shows the eQEP timing requirement and Table 6-27 shows the eQEP switching
characteristics.
Table 6-26. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements⁽¹⁾
TEST CONDITIONS
t_w(QEPP)
QEP input period
Asynchronous/synchronous
With input qualifier
t_w(INDEXH)
QEP Index Input High time
Asynchronous/synchronous
With input qualifier
t_w(INDEXL)
QEP Index Input Low time
Asynchronous/synchronous
With input qualifier
t_w(STROBH)
QEP Strobe High time
Asynchronous/synchronous
With input qualifier
t_w(STROBL)
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
(1) For an explanation of the input qualifier parameters, see Table 6-13.
MIN
2t_c(SCO)
2(1t_c(SCO) + t_w(IQSW))
2t_c(SCO)
2t_c(SCO) +t_w(IQSW)
2t_c(SCO)
2t_c(SCO) + t_w(IQSW)
2t_c(SCO)
2t_c(SCO) + t_w(IQSW)
2t_c(SCO)
2t_c(SCO) +t_w(IQSW)
Table 6-27. eQEP Switching Characteristics
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
PARAMETER
TEST CONDITIONS
MIN
t_d(CNTR)xin
Delay time, external clock to counter increment
t_{d(PXCSOUT)QEP} Delay time, QEP input edge to position compare sync output
MAX
4t_c(SCO)
6t_c(SCO)
UNIT
cycles
cycles
t_w(ADCSOCAL)
Table 6-28. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
Pulse duration, ADCSOCAO low
MIN
32t_c(HCO)
MAX UNIT
cycles
98
Electrical Specifications
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