SM320F2808-EP Datasheet, PDF (40/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 3-14. PLLCR Register Bit Definitions
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PLLCR[DIV] ⁽¹⁾
PLLSTS[CLKINDIV]
SYSCLKOUT
(CLKIN) ⁽²⁾
0000 (PLL bypass)
0
OSCCLK/2
0000 (PLL bypass)
1
OSCCLK
0001
0
(OSCCLK*1)/2
0010
0
(OSCCLK*2)/2
0011
0
(OSCCLK*3)/2
0100
0
(OSCCLK*4)/2
0101
0
(OSCCLK*5)/2
0110
0
(OSCCLK*6)/2
0111
0
(OSCCLK*7)/2
1000
0
(OSCCLK*8)/2
1001
0
(OSCCLK*9)/2
1010
0
(OSCCLK*10)/2
1011-1111
0
reserved
(1) This register is EALLOW protected.
(2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
CAUTION
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-15. Possible PLL Configuration Modes
PLL MODE
REMARKS
PLLSTS[CLKINDIV]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
0
is disabled in this mode. This can be useful to reduce system noise and for low
PLL Off
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
0
PLL Bypass
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
1
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
SYSCLKOUT
(CLKIN)
OSCCLK/2
OSCCLK
OSCCLK/2
OSCCLK
OSCCLK*n/2
3.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
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Functional Overview
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