SM320F2808-EP Datasheet, PDF (28/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
www.ti.com
3.2.9 Security
The 280x devices support high levels of security to protect the user firmware from being reverse
engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1
SARAM blocks. The security feature prevents unauthorized users from examining the memory contents
via the JTAG port, executing code from external memory or trying to boot-load some undesirable software
that would export the secure memory contents. To enable access to the secure blocks, the user must
write the correct 128-bit "KEY" value, which matches the value stored in the password locations within the
Flash.
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code
Security Password is programmed. If security is not a concern, addresses 0x3F7F80
through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are
reserved for data variables and should not contain program code.
The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
Code Security Module Disclaimer
NOTE
The Code Security Module ("CSM") included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (Texas Instruments), in accordance with its standard terms and
conditions, to conform to TI's published specifications for the warranty period applicable
for this device.
Texas Instruments DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE
CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN
THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, Texas Instruments MAKES NO
WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION
OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL Texas Instruments BE LIABLE FOR ANY CONSEQUENTIAL,
SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED,
ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE,
WHETHER OR NOT Texas Instruments HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO
LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF
BUSINESS OR OTHER ECONOMIC LOSS.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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Functional Overview
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