SM320F2808-EP Datasheet, PDF (90/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 6-11. Reset (XRS) Timing Requirements
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MIN
NOM
t_w(RSL1) ⁽¹⁾
t_w(RSL2)
t_w(WDRS)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Warm reset
8t_c(OSCCLK)
8t_c(OSCCLK)
512t_c(OSCCLK)
t_d(EX)
t_OSCST ⁽²⁾
t_h(boot-mode)
Delay time, address/data valid after XRS high
Oscillator start-up time
Hold time for boot-mode pins
1
200t_c(OSCCLK)
32t_c(OSCCLK)
10
(1) In addition to the t_w(RSL1) requirement, XRS has to be low at least for 1 ms after V_DD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
MAX
UNIT
cycles
cycles
cycles
cycles
ms
cycles
XCLKIN
X1/X2
XCLKOUT
XRS
Address/Data/
Control
(Internal)
Boot-Mode
Pins
OSCCLK * 5
User-Code Execution
Peripheral/GPIO Function
t_w(RSL2)
OSCCLK/8
User-Code Dependent
t_d(EX)
(Don’t Care)
Boot-ROM Execution Starts
GPIO Pins as Input
User-Code Execution Phase
t_{h(boot-mode)(A)}
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
90
Electrical Specifications
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