SM320F2808-EP Datasheet, PDF (5/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
6-5 Clock Timing ....................................................................................................................... 87
6-6 Power-on Reset ................................................................................................................... 89
6-7 Warm Reset........................................................................................................................ 90
6-8 Example of Effect of Writing Into PLLCR Register ........................................................................... 91
6-9 General-Purpose Output Timing ................................................................................................ 91
6-10 Sampling Mode.................................................................................................................... 92
6-11 General-Purpose Input Timing .................................................................................................. 93
6-12 IDLE Entry and Exit Timing ...................................................................................................... 94
6-13 STANDBY Entry and Exit Timing Diagram .................................................................................... 95
6-14 HALT Wake Up Using GPIOn ................................................................................................... 96
6-15 PWM Hi-Z Characteristics ....................................................................................................... 97
6-16 ADCSOCAO or ADCSOCBO Timing........................................................................................... 99
6-17 External Interrupt Timing ......................................................................................................... 99
6-18 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 102
6-19 SPI Master External Timing (Clock Phase = 1).............................................................................. 104
6-20 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 105
6-21 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 106
6-22 ADC Power-Up Control Bit Timing ............................................................................................ 108
6-23 ADC Analog Input Impedance Model ......................................................................................... 109
6-24 Sequential Sampling Mode (Single-Channel) Timing....................................................................... 110
6-25 Simultaneous Sampling Mode Timing ........................................................................................ 111
List of Figures
5