SM320F2808-EP Datasheet, PDF (106/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISOMI
SPISIMO
12
13
17
18
SPISOMI Data Is Valid
21
22
SPISIMO Data
Must Be Valid
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14
Data Valid
SPISTE^(A)
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC) before the valid SPI clock edge and
remain low for at least 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 1)
106 Electrical Specifications
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