SM320F2808-EP Datasheet, PDF (87/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
NO.
C11
C12
t_w(CIL)
t_w(CIH)
Table 6-8. XCLKIN Timing Requirements - PLL Disabled (continued)
MIN
Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)
45
Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)
45
MAX
55
55
UNIT
%
%
The possible configuration modes are shown in Table 3-15.
Table 6-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)⁽¹⁾⁽²⁾
NO.
PARAMETER
MIN
C1 t_c(XCO)
Cycle time, XCLKOUT
10
C3 t_f(XCO)
Fall time, XCLKOUT
C4 t_r(XCO)
Rise time, XCLKOUT
C5 t_w(XCOL)
Pulse duration, XCLKOUT low
H-2
C6 t_w(XCOH)
Pulse duration, XCLKOUT high
H-2
t_p
PLL lock time
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5t_c(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
TYP
2
2
C10
C8
XCLKIN^(A)
MAX
UNIT
ns
ns
ns
H+2 ns
H+2 ns
131072t_c(OSCCLK)(3) cycles
C9
C1
XCLKOUT^(B)
C3
C4
C6
C5
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-5. Clock Timing
6.7 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the V_DD pins prior to or
simultaneously with the V_DDIO pins, ensuring that the V_DD pins have reached 0.7 V before the V_DDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for t_w(RSL1) after the input clock is stable (see
Table 6-11). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 µs prior to V_DD reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n
junctions in unintended ways and produce unpredictable results.
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Electrical Specifications
87