SM320F2808-EP Datasheet, PDF (73/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 4-16. F2808 GPIO MUX Table
GPAMUX1/2 ⁽¹⁾
REGISTER
BITS
DEFAULT AT RESET
PRIMARY I/O
FUNCTION
(GPxMUX1/2 BITS =
0,0)
PERIPHERAL SELECTION
1 ⁽²⁾
PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3
(GPxMUX1/2 BITS = 0,1) (GPxMUX1/2 BITS = 1,0)
(GPxMUX1/2 BITS = 1,1)
1-0
GPIO0
3-2
GPIO1
5-4
GPIO2
7-6
GPIO3
9-8
GPIO4
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
GPAMUX1
Reserved ⁽³⁾
SPISIMOD (I/O)
Reserved ⁽³⁾
SPISOMID (I/O)
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
11-10
GPIO5
EPWM3B (O)
SPICLKD (I/O)
ECAP1 (I/O)
13-12
GPIO6
EPWM4A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
15-14
GPIO7
EPWM4B (O)
SPISTED (I/O)
ECAP2 (I/O)
17-16
GPIO8
EPWM5A (O)
CANTXB (O)
ADCSOCAO (O)
19-18
GPIO9
EPWM5B (O)
SCITXDB (O)
ECAP3 (I/O)
21-20
GPIO10
EPWM6A (O)
CANRXB (I)
ADCSOCBO (O)
23-22
GPIO11
EPWM6B (O)
SCIRXDB (I)
ECAP4 (I/O)
25-24
GPIO12
TZ1 (I)
CANTXB (O)
SPISIMOB (I/O)
27-26
GPIO13
TZ2 (I)
CANRXB (I)
SPISOMIB (I/O)
29-28
GPIO14
TZ3 (I)
SCITXDB (O)
SPICLKB (I/O)
31-30
GPIO15
TZ4 (I)
SCIRXDB (I)
SPISTEB (I/O)
GPAMUX2
1-0
GPIO16
SPISIMOA (I/O)
CANTXB (O)
TZ5 (I)
3-2
GPIO17
5-4
GPIO18
7-6
GPIO19
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
TZ6 (I)
Reserved ⁽³⁾
Reserved ⁽³⁾
9-8
GPIO20
EQEP1A (I)
SPISIMOC (I/O)
CANTXB (O)
11-10
GPIO21
EQEP1B (I)
SPISOMIC (I/O)
CANRXB (I)
13-12
GPIO22
EQEP1S (I/O)
SPICLKC (I/O)
SCITXDB (O)
15-14
GPIO23
EQEP1I (I/O)
SPISTEC (I/O)
SCIRXDB (I)
17-16
GPIO24
ECAP1 (I/O)
EQEP2A (I)
SPISIMOB (I/O)
19-18
GPIO25
ECAP2 (I/O)
EQEP2B (I)
SPISOMIB (I/O)
21-20
GPIO26
ECAP3 (I/O)
EQEP2I (I/O)
SPICLKB (I/O)
23-22
25-24
27-26
29-28
31-30
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
CANTXA (O)
EQEP2S (I/O)
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved ⁽³⁾
SPISTEB (I/O)
TZ5 (I)
TZ6 (I)
Reserved ⁽³⁾
Reserved ⁽³⁾
GPBMUX1
1-0
GPIO32
SDAA (I/OC)
EPWMSYNCI (I)
ADCSOCAO (O)
3-2
GPIO33
5-4
GPIO34
SCLA (I/OC)
Reserved ⁽³⁾
EPWMSYNCO (O)
Reserved ⁽³⁾
ADCSOCBO (O)
Reserved ⁽³⁾
(1) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
(2) This table pertains to the 2808 device. Some peripherals may not be available in the 2806 or 2801 devices. See the pin descriptions for
more detail.
(3) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
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Peripherals
73