SM320F2808-EP Datasheet, PDF (48/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
www.ti.com
4.4 Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functional
block diagram of a module. See the TMS320x280x Enhanced Capture (eCAP) Module Reference Guide
(literature number SPRU807) for more details.
The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
SYNCIn
SYNCOut
CTRPHS
(phase register−32 bit)
TSCTR
OVF
(counter−32 bit)
RST
CTR_OVF
Delta−mode
32
32
CTR [0−31]
PRD [0−31]
APWM mode
CTR [0−31]
PRD [0−31]
CMP [0−31]
PWM
compare
logic
CTR=PRD
CTR=CMP
32
CAP1
(APRD active)
LD
LD1
APRD
shadow
32
32
CMP [0−31]
32
CAP2
(ACMP active)
LD
LD2
32 ACMP
shadow
Event
qualifier
32
CAP3
(APRD shadow)
LD
LD3
Polarity
select
Polarity
select
Polarity
select
Event
Pre-scale
eCAPx
32
to PIE
48
Peripherals
CAP4
(ACMP shadow)
LD
LD4
4
Capture events
CEVT[1:4]
Interrupt
Trigger
and
Flag
control
CTR_OVF
CTR=PRD
CTR=CMP
Polarity
select
4
Continuous /
Oneshot
Capture Control
Figure 4-5. eCAP Functional Block Diagram
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