SM320F2808-EP Datasheet, PDF (86/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 6-5. TMS320x280x Clock Table and Nomenclature
On-chip oscillator
clock
t_c(OSC), Cycle time
Frequency
XCLKIN ⁽¹⁾
t_c(CI), Cycle time
Frequency
SYSCLKOUT
t_c(SCO), Cycle time
Frequency
XCLKOUT
t_c(XCO), Cycle time
Frequency
HSPCLK ⁽²⁾
t_c(HCO), Cycle time
Frequency
LSPCLK ⁽²⁾
t_c(LCO), Cycle time
Frequency
ADC clock
t_c(ADCCLK), Cycle time
Frequency
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
MIN
28.6
20
10
4
10
2
10
0.5
10
10
80
6.6 Clock Requirements and Characteristics
NOM
20 ⁽³⁾
50 ⁽³⁾
40 ⁽³⁾
25 ⁽³⁾
www.ti.com
MAX
50
35
250
100
500
100
2000
100
100
100
12.5
UNIT
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
Table 6-6. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
f_x
Input clock frequency
Crystal (X1/X2)
External oscillator/clock
source (XCLKIN or X1 pin)
Without PLL
With PLL
f_l
Limp mode clock frequency range
MIN TYP MAX UNIT
20
35
20
35
MHz
4
100
5
30
1-5
MHz
Table 6-7. XCLKIN⁽¹⁾ Timing Requirements - PLL Enabled
NO.
C8
C9
C10
C11
C12
t_c(CI)
t_f(CI)
t_r(CI)
t_w(CIL)
t_w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)
Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)
(1) This applies to the X1 pin also.
MIN
33.3
45
45
Table 6-8. XCLKIN⁽¹⁾ Timing Requirements - PLL Disabled
MAX
200
6
6
55
55
UNIT
ns
ns
ns
%
%
NO.
C8
C9
t_c(CI)
t_f(CI)
C10 t_r(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
(1) This applies to the X1 pin also.
86
Electrical Specifications
MIN
10
Up to 20 MHz
20 MHz to 100 MHz
Up to 20 MHz
20 MHz to 100 MHz
MAX
250
6
2
6
2
UNIT
ns
ns
ns
ns
ns
Submit Documentation Feedback