SM320F2808-EP Datasheet, PDF (68/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Figure 4-14 is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
RX FIFO registers
SPIRXBUF
RX FIFO _0
RX FIFO _1
−−−−−
RX FIFO _15
16
Receiver
Overrun Flag
SPISTS.7
Overrun
INT ENA
SPICTL.4
RX FIFO Interrupt
RX Interrupt
Logic
SPIRXBUF
Buffer Register
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX FIFO _1
TX FIFO _0
16
SPITXBUF
16
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
TX FIFO Interrupt
TX Interrupt
Logic
SPI INT FLAG
SPISTS.6
SPI INT
ENA
SPICTL.0
16
M
M
SPIDAT
Data Register
S
S
SW1
SPIDAT.15 − 0
Talk
SPICTL.1
M
M
S
S
SW2
SPIINT/SPIRXINT
To CPU
SPITXINT
State Control
SPI Char SPICCR.3 − 0
S
32 1 0
SPI Bit Rate
M
LSPCLK
SPIBRR.6 − 0
6543210
Master/Slave
SPICTL.2
SW3
Clock
S
Polarity
SPICCR.6
M
Clock
Phase
SPICTL.3
A. SPISTE is driven low by the master for a slave device.
Figure 4-14. SPI Module Block Diagram (Slave Mode)
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SPISIMO
SPISOMI
SPISTE^(A)
SPICLK
68
Peripherals
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