SM320F2808-EP Datasheet, PDF (39/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V_DD.
The three possible input-clock configurations are shown in Figure 3-9 through Figure 3-11
XCLKIN
X1 X2
External Clock Signal
NC
(Toggling 0 −V_DDIO)
Figure 3-9. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
NC
(Toggling 0 −V_DD)
Figure 3-10. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
C_L1
C_L2
Crystal
Figure 3-11. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
• Fundamental mode, parallel resonant
• C_L (load capacitance) = 12 pF
• C_L1 = C_L2 = 24 pF
• C_shunt = 6 pF
• ESR range = 30 to 60 Ω
Texas Instruments recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise
to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component
values that will produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
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Functional Overview
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