SM320F2808-EP Datasheet, PDF (29/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
3.2.11 External Interrupts (XINT1, XINT2, XNMI)
The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be
configured to trigger any external interrupt.
3.2.12 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the
ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. A reset or external signal can wake the device from
this mode.
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Timers:
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
PF1:
CSM:
ADC:
eCAN:
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
eCAN Mailbox and Control Registers
GPIO:
ePWM:
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
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Functional Overview
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