SM320F2808-EP Datasheet, PDF (71/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
4.11 GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-16. Because of the open drain capabilities of the I²C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for details.
GPIOLMPSEL
LPMCR0
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
Low Power
Modes Block
External Interrupt
PIE
MUX
Asynchronous
path
GPxPUD
Internal
Pullup
GPxQSEL1/2
GPxCTRL
Input
Qualification
GPIOx pin
Asynchronous path
High Impedance
Output Control
0 = Input, 1 = Output
XRS
GPxDAT (read)
N/C
00
01 ^{Peripheral 1 Input}
10 Peripheral 2 Input
11 _{Peripheral 3 Input}
GPxTOGGLE
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10 Peripheral 2 Output
11 Peripheral 3 Output
00
GPxDIR (latch)
01 Peripheral 1 Output Enable
10 Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 4-16. GPIO MUX Block Diagram
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Peripherals
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