SM320F2808-EP Datasheet, PDF (108/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
6.9.7.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
PWDNBG
www.ti.com
ADC Ready for Conversions
PWDNREF
PWDNADC
Request for
ADC
Conversion
t_d(BGR)
t_d(PWD)
Figure 6-22. ADC Power-Up Control Bit Timing
Table 6-37. ADC Power-Up Delays
PARAMETER ⁽¹⁾
MIN TYP MAX
UNIT
t_d(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
5
ms
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
t_d(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap
20
50
µs
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
1
ms
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1) Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting
t_d(BGR) ms before first conversion.
Table 6-38. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)⁽¹⁾⁽²⁾
ADC OPERATING MODE
Mode A (Operational Mode):
CONDITIONS
• BG and REF enabled
• PWD disabled
V_DDA18
30
Mode B:
• ADC clock enabled
9
• BG and REF enabled
• PWD enabled
Mode C:
• ADC clock enabled
5
• BG and REF disabled
• PWD enabled
Mode D:
• ADC clock disabled
5
• BG and REF disabled
• PWD enabled
(1) Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) V_DDA18 includes current into V_DD1A18 and V_DD2A18. V_DDA3.3 includes current into V_DDA2 and V_DDAIO.
V_DDA3.3
2
0.5
UNIT
mA
ma
20
µA
15
µA
108 Electrical Specifications
Submit Documentation Feedback