SM320F2808-EP Datasheet, PDF (36/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 3-11. PIE Configuration and Control Registers
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NAME
ADDRESS SIZE (X16)
DESCRIPTION ⁽¹⁾
PIECTRL
0x0CE0
1
PIE, Control Register
PIEACK
0x0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
6
Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
3.5.1 External Interrupts
NAME
XINT1CR
XINT2CR
reserved
XNMICR
XINT1CTR
XINT2CTR
reserved
XNMICTR
Table 3-12. External Interrupt Registers
ADDRESS
0x7070
0x7071
0x7072
0x7076
0x7077
0x7078
0x7079
0x707A
0x707E
0x707F
SIZE (x16)
1
1
5
1
1
1
5
1
XINT1 control register
XINT2 control register
XNMI control register
XINT1 counter register
XINT2 counter register
XNMI counter register
DESCRIPTION
36
Functional Overview
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