SM320F2808-EP Datasheet, PDF (35/118 Pages) Texas Instruments – Digital Signal Processors

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INT1
INT2
INT11
INT12
IFR(12:1)
(Flag)
IER(12:1)
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
INTM
(Enable)
MUX
1
0
Global
Enable
CPU
INTx
MUX
PIEACKx
(Enable/Flag)
(Enable)
PIEIERx(8:1)
(Flag)
PIEIFRx(8:1)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
From
Peripherals or
External
Interrupts
Figure 3-6. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts⁽¹⁾
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
PIE INTERRUPTS
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
XINT1
reserved
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT2
reserved
reserved
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
INT3
INT4
reserved
reserved
reserved
reserved
EPWM6_INT
(ePWM6)
reserved
EPWM5_INT
(ePWM5)
reserved
EPWM4_INT
(ePWM4)
ECAP4_INT
(eCAP4)
EPWM3_INT
(ePWM3)
ECAP3_INT
(eCAP3)
EPWM2_INT
(ePWM2)
ECAP2_INT
(eCAP2)
EPWM1_INT
(ePWM1)
ECAP1_INT
(eCAP1)
INT5
reserved
reserved
reserved
reserved
reserved
reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
INT6
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
SPITXINTC
(SPI-C)
SPIRXINTC
(SPI-C)
SPITXINTB
(SPI-B)
SPIRXINTB
(SPI-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
I2CINT2A
(I2C-A)
reserved
I2CINT1A
(I2C-A)
INT9
ECAN1_INTB ECAN0_INTB ECAN1_INTA ECAN0_INTA
(CAN-B)
(CAN-B)
(CAN-A)
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
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Functional Overview
35