SM320F2808-EP Datasheet, PDF (113/118 Pages) Texas Instruments – Digital Signal Processors

www.ti.com
6.11 Flash Timing
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 6-41. Flash Endurance
N_f Flash endurance for the array (write/erase cycles)
N_OTP OTP endurance for the array (write cycles)
-55°C to 125°C (ambient)
-55°C to 125°C (ambient)
MIN TYP
100 1000
MAX
1
UNIT
cycles
write
Table 6-42. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER ⁽¹⁾
TEST CONDITIONS
MIN TYP
Program
16-Bit Word
50
Time
16K Sector
500
8K Sector
250
4K Sector
125
Erase Time 16K Sector
10
8K Sector
10
4K Sector
10
I_DD3VFLP
V_DD3VFL current consumption during the
Erase
75
Erase/Program cycle
Program
35
I_DDP
V_DD current consumption during Erase/Program
140
cycle
I_DDIOP
V_DDIO current consumption during Erase/Program
20
cycle
(1) Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.
Table 6-43. Flash/OTP Access Timing
MAX
UNIT
µs
ms
ms
ms
S
S
S
mA
mA
mA
mA
PARAMETER ⁽¹⁾
MIN
t_a(fp)
Paged flash access time
36
t_a(fr)
Random flash access time
36
t_a(OTP)
OTP access time
60
(1) For 100 MHz, PAGE WS = 3 and RANDOM WS = 3; for 75 MHz, PAGE WS = 2, and RANDOM WS = 2.
TYP MAX
Equations to compute the page wait state and random wait state in Table 6-44 are as follows:
ƪǒ Ǔ ƫ Flash Page Wait-State +
t_a(fp)
t_c(SCO)
*1
(round up to the next highest integer) or 0, whichever is larger
ƪǒ Ǔ ƫ Flash Random Wait-State+
t_a(fr)
t_c(SCO)
* 1 (round up to the next highest integer) or 1, whichever is larger
UNIT
ns
ns
ns
Submit Documentation Feedback
Electrical Specifications 113