SM320F2808-EP Datasheet, PDF (95/118 Pages) Texas Instruments – Digital Signal Processors

www.ti.com
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 6-17. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
t_d(IDLE-XCOL)
Delay time, IDLE instruction
executed to XCLKOUT low
32t_c(SCO)
45t_c(SCO) cycles
Delay time, external wake signal
to program execution resume⁽¹⁾
cycles
• Wake up from flash
– Flash module in active
state
t_{d(WAKE-STBY) • Wake up from flash}
– Flash module in sleep
state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100t_c(SCO)
100t_c(SCO) + t_w(WAKE-INT)
1125t_c(SCO)
1125t_c(SCO) + t_w(WAKE-INT)
cycles
cycles
• Wake up from SARAM
Without input qualifier
With input qualifier
100t_c(SCO)
100t_c(SCO) + t_w(WAKE-INT)
cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
Device
Status
Wake−up
Signal
(A)
(B)
Flushing Pipeline
X1/X2 or
X1 or
XCLKIN
(C)
STANDBY
(D)
STANDBY
(E)
(F)
Normal Execution
t_w(WAKE-INT)
t_d(WAKE-STBY)
XCLKOUT
t_{d(IDLE−XCOL)}
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-13. STANDBY Entry and Exit Timing Diagram
Table 6-18. HALT Mode Timing Requirements
t_w(WAKE-GPIO) Pulse duration, GPIO wake-up signal
t_w(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1) See Table 6-11 for an explanation of t_oscst.
Submit Documentation Feedback
MIN
t_oscst + 2t_c(OSCCLK) ⁽¹⁾
t_oscst + 8t_c(OSCCLK)
NOM
MAX
UNIT
cycles
cycles
Electrical Specifications
95