SM320F2808-EP Datasheet, PDF (37/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x System Control and Interrupts Reference
Guide (literature number SPRU712).
3.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-7 shows the various clock and reset domains in the 280x devices that will be
discussed.
28x
CPU
Reset
SYSCLKOUT^(A)
Peripheral Reset
CLKIN^(A)
Watchdog
Block
PLL
OSC
XRS
X1
X2
Peripheral
Registers
System
Control
Registers
Peripheral
Registers
CPU
Timers
Clock Enables
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
Power
Modes
Control
I/O
XCLKIN
Peripheral
Registers
eCAN-A/B
I²C-A
Low-Speed Prescaler
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
I/O
GPIO
GPIOs
MUX
I/O
16 ADC inputs
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-7. Clock and Reset Domains
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Functional Overview
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