SM320F2808-EP Datasheet, PDF (91/118 Pages) Texas Instruments – Digital Signal Processors

www.ti.com
OSCCLK
SYSCLKOUT
Write to PLLCR
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t_p) is
131072 OSCCLK Cycles Long.)
(Changed CPU Frequency)
Figure 6-8. Example of Effect of Writing Into PLLCR Register
6.8 General-Purpose Input/Output (GPIO)
6.8.1 GPIO - Output Timing
t_r(GPO)
t_f(GPO)
t_fGPO
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
MIN
Rise time, GPIO switching low to high
All GPIOs
Fall time, GPIO switching high to low
All GPIOs
Toggling frequency, GPO pins
MAX
8
8
25
UNIT
ns
ns
MHz
GPIO
t_f(GPO)
t_r(GPO)
Figure 6-9. General-Purpose Output Timing
Submit Documentation Feedback
Electrical Specifications
91