SM320F2808-EP Datasheet, PDF (101/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
Table 6-32. SPI Master Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}
NO.
1 t_c(SPC)M
2 t_w(SPCH)M
t_w(SPCL)M
3 t_w(SPCL)M
t_w(SPCH)M
4 t_{d(SPCH-SIMO)M}
t_{d(SPCL-SIMO)M}
5 t_{v(SPCL-SIMO)M}
t_{v(SPCH-SIMO)M}
8 t_{su(SOMI-SPCL)M}
t_{su(SOMI-SPCH)M}
9 t_{v(SPCL-SOMI)M}
t_{v(SPCH-SOMI)M}
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
MIN
MAX
4t_c(LCO)
0.5t_c(SPC)M -10
128t_c(LCO)
0.5t_c(SPC)M
0.5t_c(SPC)M - 10
0.5t_c(SPC)M
0.5t_c(SPC)M - 10
0.5_tc(SPC)M
0.5_tc(SPC)M - 10
0.5t_c(SPC)M
10
10
0.5t_c(SPC)M -10
0.5t_c(SPC)M -10
35
35
0.25t_c(SPC)M -10
0.25t_c(SPC)M - 10
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
MIN
MAX
5t_c(LCO)
0.5t_c(SPC)M - 0.5t_c(LCO) - 10
127t_c(LCO)
0.5t_c(SPC)M - 0.5t_c(LCO)
UNIT
ns
ns
0.5t_c(SPC)M - 0.5t_c(LCO) - 10
0.5t_c(SPC)M - 0.5t_c(LCO)
0.5t_c(SPC)M + 0.5t_c(LCO)-10
0.5t_c(SPC)M + 0.5t_c(LCO)
ns
0.5t_c(SPC)M + 0.5t_c(LCO)- 10
0.5t_c(SPC)M + 0.5t_c(LCO)
10 ns
10
0.5t_c(SPC)M + 0.5t_c(LCO) -10
0.5t_c(SPC)M + 0.5t_c(LCO) -10
35
ns
35
ns
0.5t_c(SPC)M- 0.5t_c(LCO)- 10
0.5t_c(SPC)M- 0.5t_c(LCO)- 10
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) t_c(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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Electrical Specifications 101