SM320F2808-EP Datasheet, PDF (102/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
SPISIMO
SPISOMI
1
2
3
4
5
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
www.ti.com
SPISTE^(A)
A. In the master mode, SPISTE goes active 0.5t_c(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5t_c(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Master Mode External Timing (Clock Phase = 0)
102 Electrical Specifications
Submit Documentation Feedback