SM320F2808-EP Datasheet, PDF (31/118 Pages) Texas Instruments – Digital Signal Processors

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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
The 280x devices support the following serial communication peripherals:
eCAN:
SPI:
SCI:
I²C:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO for
reducing interrupt servicing overhead.
The inter-integrated circuit (I²C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I²C-bus) specification version
2.1 and connected by way of an I²C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I²C module.
On the 280x, the I²C contains a 16-level receive and transmit FIFO for reducing interrupt
servicing overhead.
3.3 Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
Peripheral
Frame 1
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-6
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-7
Peripheral
Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-8
Table 3-6. Peripheral Frame 0 Registers⁽¹⁾⁽²⁾
NAME
ADDRESS RANGE SIZE (x16) ACCESS TYPE⁽³⁾
Device Emulation Registers
0x0880
0x09FF
384
EALLOW protected
FLASH Registers⁽⁴⁾
0x0A80
0x0ADF
96
EALLOW protected
CSM Protected
Code Security Module Registers
0x0AE0
0x0AEF
16
EALLOW protected
ADC Result Registers
(dual-mapped)
0xB00
0xB0F
16
Not EALLOW protected
CPU-TIMER0/1/2 Registers
0x0C00
0x0C3F
64
Not EALLOW protected
PIE Registers
0x0CE0
0x0CFF
32
Not EALLOW protected
PIE Vector Table
0x0D00
0x0DFF
256
EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).
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Functional Overview
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