SM320F2808-EP Datasheet, PDF (70/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
System Control
Block
I2CAENCLK
GPIO
MUX
SDAA
SCLA
I²C−A
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C28X CPU
SYSCLKOUT
SYSRS
Control
Data[16]
Data[16]
Addr[16]
I2CINT1A
I2CINT2A
PIE
Block
A. The I²C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I²C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I²C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-15. I²C Peripheral Module Interfaces
The registers in Table 4-14 configure and control the I²C port operation.
Table 4-14. I²C-A Registers
NAME
I2COAR
I2CIER
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
-
DESCRIPTION
I²C own address register
I²C interrupt enable register
I²C status register
I²C clock low-time divider register
I²C clock high-time divider register
I²C data count register
I²C data receive register
I²C slave address register
I²C data transmit register
I²C mode register
I²C interrupt source register
I²C prescaler register
I²C FIFO transmit register
I²C FIFO receive register
I²C receive shift register (not accessible to the CPU)
I²C transmit shift register (not accessible to the CPU)
70
Peripherals
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