SM320F2808-EP Datasheet, PDF (72/118 Pages) Texas Instruments – Digital Signal Processors

SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
SGLS316A – MARCH 2006 – REVISED FEBRUARY 2007
www.ti.com
The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable Register (GPIO0 to 31)
reserved
0x6F8E
0x6F8F
2
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 35)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
GPBQSEL2
0x6F94
2
reserved
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 35)
GPBMUX2
0x6F98
2
reserved
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 35)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 35)
reserved
0x6F9E
0x6F9F
2
reserved
reserved
0x6FA0
0x6FBF
32
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
2
GPIO Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO Data Register (GPIO32 to 35)
GPBSET
0x6FCA
2
GPIO Data Set Register (GPIO32 to 35)
GPBCLEAR
0x6FCC
2
GPIO Data Clear Register (GPIO32 to 35)
GPBTOGGLE
0x6FCE
2
GPIO Data Toggle Register (GPIO32 to 35)
reserved
0x6FD0
0x6FDF
16
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
reserved
0x6FE3
0x6FE7
5
GPIOLPMSEL
0x6FE8
2
LPM GPIO Select Register (GPIO0 to 31)
reserved
0x6FEA
0x6FFF
22
72
Peripherals
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