SMJ320C6203 Datasheet, PDF (78/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs^†
(see Figure 54)
NO.
PARAMETER
1 tw(PDH)
Pulse duration, PD high
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
1
PD
MIN MAX UNIT
*2P–3
ns
Figure 54. Power-Down Timing
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 55)
NO.
1 tc(TCK)
Cycle time, TCK
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high
*This parameter is not production tested.
MIN MAX UNIT
*35
ns
*11
ns
*9
ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 55)
NO.
PARAMETER
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid
*This parameter is not production tested.
MIN MAX UNIT
*–4.5 *13.5 ns
TCK
TDO
TDI/TMS/TRST
1
2
2
4
3
Figure 55. JTAG Test-Port Timing
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