SMJ320C6203 Datasheet, PDF (66/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
XAS
XW/R^†
XW/R^†
XBLAST^‡
XBE[3:0]/XA[5:2]^§
5
XD[31:0]
XRDY
XBOFF
1
1
2
4
6
Addr
D1
11
2
4
7
8
D2
12
15
14
XHOLD^¶
XHOLDA^¶
XHOLD#
XHOLDA#
† _{XW/R input/output polarity selected at boot}
‡ _{XBLAST output polarity is always active low.}
§ _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
¶ _{Internal arbiter enabled}
# _{External arbiter enabled}
|| _{This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 44 and Figure 45.}
Figure 41. C62x as Bus Master—BOFF Operation^||
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