SMJ320C6203 Datasheet, PDF (5/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

functional and CPU (DSP core) block diagram
SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
SDRAM or
SBSRAM
32
SRAM
ROM/FLASH
I/O Devices
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Synchronous
FIFOs
32
I/O Devices
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
External Memory
Interface (EMIF)
C6203 Digital Signal Processors
Program
Access/Cache
Controller
Internal Program Memory
2 Blocks Program/Cache
(384K Bytes)
Timer 0
Timer 1
Multichannel
Buffered Serial
Port 0
Multichannel
Buffered Serial
Port 1
Multichannel
Buffered Serial
Port 2
Interrupt
Selector
C62x CPU (DSP Core)
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
Data Path B
A Register File
B Register File
Control
Registers
Control
Logic
Test
In-Circuit
Emulation
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2 ^Interrupt
Control
Peripheral Control Bus
Data
Access
Controller
Internal Data
Memory
(512K Bytes)
Expansion
Bus
32-Bit
Direct Memory
Access Controller
(DMA)
(See Table 1)
PLL
(x1, x4, x6, x7, x8,
x9, x10, x11, x12)^†
Power-
Down
Logic
Boot Configuration
† _{For additional details on the PLL clock module and specific options for the C6203 device, see Table 1 and the Clock PLL section of this data sheet.}
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