SMJ320C6203 Datasheet, PDF (21/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
Signal Descriptions (Continued)
SIGNAL
NAME
PIN
NO.
GLP
TYPE^†
DESCRIPTION
EXPANSION BUS (CONTINUED)
XCE3
XCE2
XCE1
XCE0
D3
G6
Expansion bus I/O port memory space enables
O/Z • Enabled by bits 28, 29, and 30 of the word address
D4
• Only one asserted during any I/O port data access
E4
XBE3/XA5
XBE2/XA4
XBE1/XA3
XBE0/XA2
F6
F7
Expansion bus multiplexed byte-enable control/address signals
I/O/Z • Act as byte-enable for host-port operation
B5
• Act as address for I/O port operation
C7
XOE
B7
O/Z Expansion bus I/O port output-enable
XRE
B8
O/Z Expansion bus I/O port read-enable
XWE/XWAIT
D7
O/Z Expansion bus I/O port write-enable and host-port wait signals
XCS
D8
I
Expansion bus host-port chip-select input
XAS
G9
I/O/Z Expansion bus host-port address strobe
XCNTL
A9
I
Expansion bus host control. XCNTL selects between expansion bus address or data register.
XW/R
F9
I/O/Z Expansion bus host-port write/read-enable. XW/R polarity is selected at reset.
XRDY
F4
I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high)
XBLAST
C5
I/O/Z Expansion bus host-port burst last-polarity selected at reset
XBOFF
C10
I
Expansion bus back off
XHOLD
C4
I/O/Z Expansion bus hold request
XHOLDA
D6
I/O/Z Expansion bus hold acknowledge
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
V18
CE2
W18
Memory space enables
O/Z • Enabled by bits 24 and 25 of the word address
CE1
T15
• Only one asserted during any external data access
CE0
U18
BE3
R15
Byte-enable control
BE2
BE1
V19
U20
O/Z
• Decoded from the two lowest bits of the internal address
• Byte-write enables for most types of memory
BE0
V16
• Can be directly connected to SDRAM read and write mask signal (SDQM)
† _{I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground}
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