SMJ320C6203 Datasheet, PDF (52/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles^† (see Figure 27)
NO.
3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
MIN MAX UNIT
*P
ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles^†‡
(see Figure 27)
NO.
PARAMETER
MIN MAX UNIT
1 td(HOLDL-EMHZ)
Delay time, HOLD low to EMIF Bus high impedance
*3P
§ _ns
2 td(EMHZ-HOLDAL)
Delay time, EMIF Bus high impedance to HOLDA low
*0 *2P ns
4 td(HOLDH-EMLZ)
Delay time, HOLD high to EMIF Bus low impedance
*3P *7P ns
5 td(EMLZ-HOLDAH)
Delay time, EMIF Bus low impedance to HOLDA high
*0 *2P ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.}
§ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with}
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
3
HOLD
2
5
HOLDA
EMIF Bus^‡
1
C6203
4
C6203
‡ _{EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.}
Figure 27. HOLD/HOLDA Timing
RESET TIMING
timing requirements for reset^† (see Figure 28)
NO.
MIN MAX UNIT
1 tw(RST)
Width of the RESET pulse (PLL stable)^¶
Width of the RESET pulse (PLL needs to sync up)#
*10P
ns
*250
µs
10 tsu(XD)
11 th(XD)
Setup time, XD configuration bits valid before RESET high||
Hold time, XD configuration bits valid after RESET high||
*5P
ns
*5P
ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
¶ _{This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL}
are stable.
# _{This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only (it does not apply to CLKMODE x1). The RESET signal is not connected}
internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration
has been changed. During that time, RESET must be asserted to ensure proper device operation. See the Clock PLL section for PLL lock times.
|| _{XD[31:0] are the boot configuration pins during device reset.}
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