SMJ320C6203 Datasheet, PDF (19/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
Signal Descriptions
SIGNAL
NAME
PIN
NO.
GLP
TYPE^†
DESCRIPTION
CLOCK/PLL
CLKIN
D10
I
Clock input
CLKOUT1
Y17
O Clock output at full device speed
CLKOUT2
Clock output at half (1/2) of device speed
Y16
O
• Used for synchronous memory interface
CLKMODE0
C12
CLKMODE1
G10
CLKMODE2
G12
I
Clock mode selects
• Selects what multiply factors of the input clock frequency the CPU frequency
I
equals.
For more details on the CLKMODE pins and the PLL multiply factors for the C6203 device, see the
I
Clock PLL section of this data sheet.
PLLV^‡
PLLG^‡
B11
A^§ PLL analog VCC connection for the low-pass filter
A11
A^§ PLL analog GND connection for the low-pass filter
PLLF^‡
G11
A^§ PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
W5
I
JTAG test-port mode select (features an internal pullup)
TDO
R8
O/Z JTAG test-port data out
TDI
W4
I
JTAG test-port data in (features an internal pullup)
TCK
V5
I
JTAG test-port clock
TRST
EMU1
EMU0
R7
I
JTAG test-port reset (features an internal pulldown)
T7
I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor^¶
Y5
I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor^¶
RESET AND INTERRUPTS
RESET
J4
I
Device reset
NMI
K2
I
Nonmaskable interrupt
• Edge-driven (rising edge)
EXT_INT7
R4
External interrupts
EXT_INT6
EXT_INT5
P6
T2
I
• Edge-driven
• Polarity independently selected via the External Interrupt Polarity Register bits
EXT_INT4
T3
(EXTPOL.[3:0])
IACK
R2
O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
P4
INUM2
INUM1
P1
Active interrupt identification number
O • Valid during IACK for all active interrupts (not just external)
P2
• Encoding order follows the interrupt-service fetch-packet ordering
INUM0
N6
† _{I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground}
‡ _{PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.}
§ _{A = Analog Signal (PLL Filter)}
¶ _{For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0}
with a dedicated 20-kΩ resistor.
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