SMJ320C6203 Datasheet, PDF (42/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for XFCLK^†‡ (see Figure 14)
NO.
PARAMETER
1 tc(XFCK)
Cycle time, XFCLK
2 tw(XFCKH) Pulse duration, XFCLK high
3 tw(XFCKL)
Pulse duration, XFCLK low
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns.}
‡ _{D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable}
MIN
*D x P – 0.7
*(D/2) x P – 0.7
*(D/2) x P – 0.7
MAX
*D x P + 0.7
*(D/2) x P + 0.7
*(D/2) x P + 0.7
UNIT
ns
ns
ns
XFCLK
1
2
3
Figure 14. XFCLK Timings
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles^§¶#|| (see Figure 15 – Figure 18)
NO.
MIN
MAX UNIT
3 tsu(EDV-AREH)
Setup time, EDx valid before ARE high
4 th(AREH-EDV)
Hold time, EDx valid after ARE high
6 tsu(ARDYH-AREL) Setup time, ARDY high before ARE low
7 th(AREL-ARDYH) Hold time, ARDY high after ARE low
1
ns
4.9
ns
–[(RST – 3) x P – 6]
ns
(RST – 3) x P + 2
ns
9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low
10 th(AREL-ARDYL) Hold time, ARDY low after ARE low
–[(RST – 3) x P – 6]
ns
(RST – 3) x P + 2
ns
11 tw(ARDYH)
Pulse width, ARDY high
*2P
ns
15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low
16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low
–[(WST – 3) x P – 6]
ns
(WST – 3) x P + 2
ns
18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low
–[(WST – 3) x P – 6]
ns
19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low
(WST – 3) x P + 2
ns
*This parameter is not production tested.
§ _{To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold}
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
¶ _{RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are}
programmed via the EMIF CE space control registers.
# _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
|| _{The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.}
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