SMJ320C6203 Datasheet, PDF (53/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
RESET TIMING (CONTINUED)
SGUS033 – FEBRUARY 2002
switching characteristics over recommended operating conditions during reset^†‡ (see Figure 28)
NO.
PARAMETER
MIN MAX UNIT
2 td(RSTL-CKO2IV)
Delay time, RESET low to CLKOUT2 invalid
*P
ns
3 td(RSTH-CKO2V)
Delay time, RESET high to CLKOUT2 valid
*4P ns
4 td(RSTL-HIGHIV)
Delay time, RESET low to high group invalid
*P
ns
5 td(RSTH-HIGHV)
Delay time, RESET high to high group valid
*4P ns
6 td(RSTL-LOWIV)
Delay time, RESET low to low group invalid
*P
ns
7 td(RSTH-LOWV)
Delay time, RESET high to low group valid
*4P ns
8 td(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
*P
ns
9 td(RSTH-ZV)
Delay time, RESET high to Z group valid
*4P ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{High group consists of:}
XFCLK, HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
CLKOUT1
RESET
1
10
11
2
3
CLKOUT2
4
5
HIGH GROUP^‡
6
7
LOW GROUP^‡
8
9
Z GROUP^‡
XD[31:0]^§
Boot Configuration
‡ _{High group consists of:}
XFCLK, HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,
FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,
and XHOLDA
§ _{XD[31:0] are the boot configuration pins during device reset.}
Figure 28. Reset Timing
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