SMJ320C6203 Datasheet, PDF (64/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
timing requirements with C62x as bus master (see Figure 39, Figure 40, and Figure 41)
NO.
MIN MAX UNIT
9 tsu(XDV-XCKIH)
10 th(XCKIH-XDV)
11 tsu(XRY-XCKIH)
12 th(XCKIH-XRY)
Setup time, XDx valid before XCLKIN high
Hold time, XDx valid after XCLKIN high
Setup time, XRDY valid before XCLKIN high^†
Hold time, XRDY valid after XCLKIN high^†
3.5
ns
2.8
ns
3.5
ns
2.8
ns
14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high
15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high
† _{XRDY operates as active-low ready input/output during host-port accesses.}
3.5
ns
2.8
ns
switching characteristics over recommended operating conditions with C62x as bus master^‡
(see Figure 39, Figure 40, and Figure 41)
NO.
PARAMETER
1 td(XCKIH-XASV)
2 td(XCKIH-XWRV)
3 td(XCKIH-XBLTV)
4 td(XCKIH-XBEV)
Delay time, XCLKIN high to XAS valid
Delay time, XCLKIN high to XW/R valid^§
Delay time, XCLKIN high to XBLAST valid^¶
Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid#
5 td(XCKIH-XDLZ)
Delay time, XCLKIN high to XDx low impedance
6 td(XCKIH-XDV)
Delay time, XCLKIN high to XDx valid
7 td(XCKIH-XDIV)
Delay time, XCLKIN high to XDx invalid
8 td(XCKIH-XDHZ)
Delay time, XCLKIN high to XDx high impedance
13 td(XCKIH-XWTV)
Delay time, XCLKIN high to XWE/XWAIT valid||
*This parameter is not production tested.
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{XW/R input/output polarity selected at boot.}
¶ _{XBLAST output polarity is always active low.}
# _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
|| _{XWE/XWAIT operates as XWAIT output signal during host-port accesses.}
MIN MAX UNIT
*5
17 ns
*5
17 ns
*5
17 ns
*5
17 ns
*0
ns
17 ns
*5
ns
*4P ns
*5
17 ns
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