SMJ320C6203 Datasheet, PDF (48/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
NO.
7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high
MIN MAX
1.2
2.9
UNIT
ns
ns
switching characteristics over recommended operating conditions for synchronous DRAM cycles
for C6203B Rev. 2^†‡ (see Figure 21–Figure 26)
NO.
PARAMETER
MIN MAX UNIT
1 tosu(CEV-CKO2H)
Output setup time, CEx valid before CLKOUT2 high
P – 0.9
ns
2 toh(CKO2H-CEV)
Output hold time, CEx valid after CLKOUT2 high
*P – 4
ns
3 tosu(BEV-CKO2H)
Output setup time, BEx valid before CLKOUT2 high
P – 0.9
ns
4 toh(CKO2H-BEIV)
Output hold time, BEx invalid after CLKOUT2 high
*P – 4
ns
5 tosu(EAV-CKO2H)
Output setup time, EAx valid before CLKOUT2 high
P – 0.9
ns
6 toh(CKO2H-EAIV)
Output hold time, EAx invalid after CLKOUT2 high
*P – 4
ns
9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high
P – 0.9
ns
10 toh(CKO2H-CASV)
11 tosu(EDV-CKO2H)
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high^§
*P – 4
ns
P – 1.5
ns
12 toh(CKO2H-EDIV)
Output hold time, EDx invalid after CLKOUT2 high
*P – 4
ns
13 tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE valid before CLKOUT2 high
P – 0.9
ns
14 toh(CKO2H-WEV)
Output hold time, SDWE/SSWE valid after CLKOUT2 high
*P – 4
ns
15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high
P – 0.9
ns
16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high
*P – 4
ns
17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high
P – 0.9
ns
18 toh(CKO2H-RASV)
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
*P – 4
ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.}
§ _{For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate}
the ED enable time.
48
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443