SMJ320C6203 Datasheet, PDF (46/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 19)
NO.
7 tsu(EDV-CKO2H)
8 th(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
MIN MAX UNIT
2.0
ns
2.0
ns
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles^†‡ (see Figure 19 and Figure 20)
NO.
PARAMETER
MIN
MAX UNIT
1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high
2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high
3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high
4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high
5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high
6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high
9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high
10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high
11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high
12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high
13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high^§
14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high
15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high
P – 0.8
ns
*P – 4
ns
P – 0.8
ns
*P – 4
ns
P – 0.8
ns
*P – 4
ns
P – 0.8
ns
*P – 4
ns
P – 0.8
ns
*P – 4
ns
P – 1.2
ns
*P – 4
ns
P – 0.8
ns
16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high
*P – 4
ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.}
§ _{For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate}
the ED enable time.
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