SMJ320C6203 Datasheet, PDF (39/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers
may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 18 and Figure 10).
Figure 10 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 18. IBIS Timing Parameters Example (see Figure 10)
NO.
DESCRIPTION
1 Clock route delay
2 Minimum DSP hold time
3 Minimum DSP setup time
4 External device hold time requirement
5 External device setup time requirement
6 Control signal route delay
7 External device hold time
8 External device access time
9 DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
CLKOUT2
(Output from DSP)
CLKOUT2
(Input to External Device)
Control Signals^†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals^‡
(Output from External Device)
Data Signals^‡
(Input to DSP)
1
2
3
4
5
6
7
8
9
10
11
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 10. IBIS Input/Output Timings
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