SMJ320C6203 Datasheet, PDF (55/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
EXPANSION BUS SYNCHRONOUS FIFO TIMING
SGUS033 – FEBRUARY 2002
timing requirements for synchronous FIFO interface (see Figure 30, Figure 31, and Figure 32)
NO.
5 tsu(XDV-XFCKH)
6 th(XFCKH-XDV)
Setup time, read XDx valid before XFCLK high
Hold time, read XDx valid after XFCLK high
MIN
3
2.5
MAX
UNIT
ns
ns
switching characteristics over recommended operating conditions for synchronous FIFO
interface (see Figure 30, Figure 31, and Figure 32)
NO.
PARAMETER
1 td(XFCKH-XCEV)
2 td(XFCKH-XAV)
Delay time, XFCLK high to XCEx valid
Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid^†
3 td(XFCKH-XOEV)
Delay time, XFCLK high to XOE valid
4 td(XFCKH-XREV)
7 td(XFCKH-XWEV)
Delay time, XFCLK high to XRE valid
Delay time, XFCLK high to XWE/XWAIT^‡ valid
8 td(XFCKH-XDV)
Delay time, XFCLK high to XDx valid
9 td(XFCKH-XDIV)
Delay time, XFCLK high to XDx invalid
*This parameter is not production tested.
† _{XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.}
‡ _{XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.}
MIN
*–1.5
*–1.5
*–1.5
*–1.5
*–1.5
*–1.5
MAX
4.5
4.5
4.5
4.5
4.5
4.5
UNIT
ns
ns
ns
ns
ns
ns
ns
XFCLK
XCE3
See Note A
XBE[3:0]/XA[5:2]
See Note B
XOE
1
2
XA1
XA2
XA3
3
1
XA4
4
4
XRE
XWE/XWAIT
See Note C
XD[31:0]
6
5
D1
D2
D3
NOTES: A. FIFO read (glueless) mode only available in XCE3.
B. XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.
C. XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.
Figure 30. FIFO Read Timing (Glueless Read Mode)
2
3
D4
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