SMJ320C6203 Datasheet, PDF (54/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles^† (see Figure 29)
NO.
2 tw(ILOW)
Width of the interrupt pulse low
3 tw(IHIGH)
Width of the interrupt pulse high
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
MIN MAX UNIT
*2P
ns
*2P
ns
switching characteristics over recommended operating conditions during interrupt response
cycles^†‡ (see Figure 29)
NO.
PARAMETER
MIN
1 tR(EINTH _{– IACKH)} Response time, EXT_INTx high to IACK high
*9P
4 td(CKO2L-IACKV)
Delay time, CLKOUT2 low to IACK valid
*–1.5
5 td(CKO2L-INUMV)
Delay time, CLKOUT2 low to INUMx valid
*–2.0
6 td(CKO2L-INUMIV)
Delay time, CLKOUT2 low to INUMx invalid
*–2.0
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{When CLKOUT2 is in half (1/2) mode (see CLKOUT2 in Signal Descriptions table), timings are based on falling edges}
MAX
*10
*10
*10
UNIT
ns
ns
ns
ns
CLKOUT2 (1/4)
[C6203C only]
1
CLKOUT2 (1/2)
2
3
EXT_INTx, NMI
Intr Flag
IACK
INUMx
4
4
5
6
Interrupt Number
Figure 29. Interrupt Timing
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