SMJ320C6203 Datasheet, PDF (35/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

clock PLL (continued)
3.3V
PLLV
CLKMODE0
CLKMODE1
CLKMODE2
CLKIN
SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
PLLMULT
PLL
PLLCLK
CLKIN
LOOP FILTER
Internal to C6203
1
CPU
0
CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
Table 16. PLL Multiply and Bypass (x1) Options^†
BIT
(PIN NO.)
CLKMODE2
(G12)
CLKMODE1
(G10)
CLKMODE0
(C12)
0
0
0
0
0
1
0
1
0
0
1
1
Value
1
0
0
1
0
1
1
1
0
1
1
1
† _{f(CPU Clock) = f(CLKIN) x (PLL mode)}
Table 17. SMJ320C6203 PLL Component Selection Table^†
DEVICES AND PLL
CLOCK OPTIONS
C6203 (GLP)
Bypass (x1)
x4
x8
x10
x6
x9
x7
x11
CLKMODE
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
CLKOUT2
RANGE
(MHz)
R1 [±1%]
C1 [±10%]
C2 [±10%]
(Revision No.) (Revision No.) (Revision No.)
TYPICAL
LOCK TIME
(µs)
x4
32.5–75
x6
21.7–50
x7
18.6–42.9
x8
16.3–37.5
130–300
65–150
45.3 Ω
47 nF
10 pF
75
x9
14.4–33.3
x10
13–30
x11
11.8–27.3
† _{Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if}
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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