SMJ320C6203 Datasheet, PDF (65/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)
XCLKIN
XAS
1
1
2
2
XW/R^†
XW/R^†
XBLAST^‡
3
3
XBE[3:0]/XA[5:2]^§
XD[31:0]
4
4
BE
5
9
7
6
8
10
AD
D1
D2
D3
D4
XRDY
XWE/XWAIT^¶
11
12
13
13
† _{XW/R input/output polarity selected at boot}
‡ _{XBLAST output polarity is always active low.}
§ _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
¶ _{XWE/XWAIT operates as XWAIT output signal during host-port accesses.}
Figure 39. C62x as Bus Master—Read
XCLKIN
XAS
1
1
XW/R^†
2
XW/R^†
XBLAST^‡
XBE[3:0]/XA[5:2]^§
XD[31:0]
XRDY
4
6
5
Addr
D1
D2
11
XWE/XWAIT^¶
† _{XW/R input/output polarity selected at boot}
‡ _{XBLAST output polarity is always active low.}
§ _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
¶ _{XWE/XWAIT operates as XWAIT output signal during host-port accesses.}
Figure 40. C62x as Bus Master—Write
D3
13
2
3
3
4
7
8
D4
12
13
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