SMJ320C6203 Datasheet, PDF (70/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP^†‡ (see Figure 46)
NO.
2 tc(CKRX)
3 tw(CKRX)
5 tsu(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
MIN
2P^§
*P–1^¶
9
2
MAX
UNIT
ns
ns
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR int
6
ns
CLKR ext
4
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int
8
ns
CLKR ext
0.5
8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
3
ns
CLKR ext
5
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low
CLKX int
9
ns
CLKX ext
2
11 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
6
ns
CLKX ext
4
*This parameter is not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings}
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶ _{The minimum CLKR/X pulse duration is either (P–1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use}
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P–1) = 9 ns as the minimum CLKR/X pulse
duration.
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