SMJ320C6203 Datasheet, PDF (56/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XFCLK
XCEx
XBE[3:0]/XA[5:2]^†
1
2
XA1
XA2
XA3
1
2
XA4
3
XOE
4
XRE
3
4
XWE/XWAIT^‡
XD[31:0]
6
5
D1
D2
D3
D4
† _{XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.}
‡ _{XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.}
Figure 31. FIFO Read Timing
XFCLK
XCEx
XBE[3:0]/XA[5:2]^†
XOE
XRE
XWE/XWAIT^‡
1
2
XA1
XA2
XA3
7
XD[31:0]
8
D1
D2
D3
† _{XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.}
‡ _{XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.}
Figure 32. FIFO Write Timing
1
2
XA4
7
9
D4
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