SMJ320C6203 Datasheet, PDF (75/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 50)
MASTER
NO.
MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high
*12
5 th(CKXH-DRV) Hold time, DR valid after CLKX high
*4
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
SLAVE
MIN MAX
*2 – 3P
*5 + 6P
UNIT
ns
ns
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 50)
NO.
1 th(CKXH-FXL)
2 td(FXL-CKXL)
3 td(CKXL-DXV)
6 tdis(CKXH-DXHZ)
PARAMETER
Hold time, FSX low after CLKX high^¶
Delay time, FSX low to CLKX low#
Delay time, CLKX low to DX valid
Disable time, DX high impedance following last data bit
from CLKX high
MASTER^§
MIN MAX
*T – 2 *T + 3
*H – 2 *H + 3
*–4
*4
SLAVE
MIN
MAX
*3P + 4 *5P + 17
UNIT
ns
ns
ns
*H – 2 *H + 3
ns
7 tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
*P + 3 *3P + 17 ns
8 td(FXL-DXV)
Delay time, FSX low to DX valid
*2P + 2 *4P + 17 ns
*This parameter is not production tested.
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
§ _{S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)}
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
The maximum transfer rate for SPI mode is limited to the above AC timing constraints.
¶ _{FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX}
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock}
(CLKX).
CLKX
FSX
DX
DR
1
2
7
6
Bit 0
Bit 0
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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