SMJ320C6203 Datasheet, PDF (14/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
DMA synchronization events
The C6203 DMA supports up to four independent programmable DMA channels, plus an auxiliary channel used
for servicing the HPI module. The four main DMA channels can be read/write synchronized based on the events
shown in Table 13. Selection of these events is done via the RSYNC and WSYNC fields in the Primary Control
registers of the specific DMA channel. For more detailed information on the DMA module, associated channels,
and event-synchronization, see the Direct Memory Access (DMA) Controller chapter of the TMS320C6000
Peripherals Reference Guide (literature number SPRU190).
Table 13. 320C6203 DMA Synchronization Events
DMA EVENT
NUMBER
(BINARY)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011 – 11111
EVENT NAME
Reserved
TINT0
TINT1
SD_INT
EXT_INT4
EXT_INT5
EXT_INT6
EXT_INT7
DMA_INT0
DMA_INT1
DMA_INT2
DMA_INT3
XEVT0
REVT0
XEVT1
REVT1
DSP_INT
XEVT2
REVT2
Reserved
EVENT DESCRIPTION
Reserved
Timer 0 interrupt
Timer 1 interrupt
EMIF SDRAM timer interrupt
External interrupt pin 4
External interrupt pin 5
External interrupt pin 6
External interrupt pin 7
DMA channel 0 interrupt
DMA channel 1 interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
Host processor-to-DSP interrupt
McBSP2 transmit event
McBSP2 receive event
Reserved. Not used.
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