SMJ320C6203 Datasheet, PDF (71/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP^†‡ (see Figure 46)
NO.
PARAMETER
MIN MAX UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
2 tc(CKRX)
3 tw(CKRX)
4 td(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR
valid
CLKR/X int
CLKR/X int
CLKR int
*4
*16 ns
*2P^§¶
ns
*C – 2# *C + 2# ns
*–3
*3 ns
9 td(CKXH-FXV)
Delay time, CLKX high to internal FSX
valid
CLKX int
CLKX ext
*–3
3
ns
*–3
9
Disable time, DX high impedance following last data bit from
12 tdis(CKXH-DXHZ) _{CLKX high}
CLKX int
CLKX ext
*–1
*5
ns
*2
*9
13 td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
CLKX ext
*–1
*4
ns
*2
*11
14 td(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay 0
(XDATDLY = 00b) mode.
FSX int
FSX ext
*–1
*5
ns
*0
*10
*This parameter is not production tested.
† _{CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.}
‡ _{Minimum delay times also represent minimum output hold times.}
§ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
¶ _{The maximum bit rate for the C6203 device is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings}
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
# _{C = H or L}
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
71