SMJ320C6203 Datasheet, PDF (61/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING
timing requirements with external device as bus master (see Figure 37 and Figure 38)
NO.
1 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high
2 th(XCKIH-XCS)
Hold time, XCS valid after XCLKIN high
3 tsu(XAS-XCKIH)
4 th(XCKIH-XAS)
Setup time, XAS valid before XCLKIN high
Hold time, XAS valid after XCLKIN high
5 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high
6 th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high
7 tsu(XWR-XCKIH) Setup time, XW/R valid before XCLKIN high^†
8 th(XCKIH-XWR)
Hold time, XW/R valid after XCLKIN high^†
9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high^‡
10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high^‡
16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high^§
17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high^§
18 tsu(XD-XCKIH)
Setup time, XDx valid before XCLKIN high
19 th(XCKIH-XD)
Hold time, XDx valid after XCLKIN high
† _{XW/R input/output polarity selected at boot.}
‡ _{XBLAST input polarity selected at boot}
§ _{XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.}
MIN MAX
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
3.5
2.8
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating conditions with external device as bus
master^¶ (see Figure 37 and Figure 38)
NO.
PARAMETER
11 td(XCKIH-XDLZ)
Delay time, XCLKIN high to XDx low impedance
12 td(XCKIH-XDV)
Delay time, XCLKIN high to XDx valid
13 td(XCKIH-XDIV)
Delay time, XCLKIN high to XDx invalid
14 td(XCKIH-XDHZ)
15 td(XCKIH-XRY)
Delay time, XCLKIN high to XDx high impedance
Delay time, XCLKIN high to XRDY invalid#
20 td(XCKIH-XRYLZ)
21 td(XCKIH-XRYHZ)
Delay time, XCLKIN high to XRDY low impedance
Delay time, XCLKIN high to XRDY high impedance#
*This parameter is not production tested.
¶ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
# _{XRDY operates as active-low ready input/output during host-port accesses.}
MIN
*0
*5
*5
*5
*2P + 5
MAX
17
*4P
*17
*17
*3P + 17
UNIT
ns
ns
ns
ns
ns
ns
ns
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