SMJ320C6203 Datasheet, PDF (2/81 Pages) Texas Instruments – FIXED POINT SIGNAL PROCESSOR

SMJ320C6203
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SGUS033 – FEBRUARY 2002
Table of Contents
GLP BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . 2
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
functional and CPU (DSP core) block diagram . . . . . . . . . 5
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 6
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . 9
DMA synchronization events . . . . . . . . . . . . . . . . . . . . . . . 14
interrupt sources and interrupt selector . . . . . . . . . . . . . . 15
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 16
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 36
absolute maximum ratings over operating case
temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
recommended operating conditions . . . . . . . . . . . . . . . . . 37
electrical characteristics over recommended ranges
of supply voltage and operating case temperature . . 37
parameter measurement information . . . . . . . . . . . . . . . . 38
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . 38
timing parameters and board routing analysis . . . . . . 39
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 42
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 46
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 48
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 54
expansion bus synchronous FIFO timing . . . . . . . . . . . . 55
expansion bus asynchronous peripheral timing . . . . . . 57
expansion bus synchronous host-port timing . . . . . . . . 61
expansion bus asynchronous host-port timing . . . . . . . 67
XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 69
multichannel buffered serial port timing . . . . . . . . . . . . . 70
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 77
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
GLP BGA package (bottom view)
GLP 429-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW)
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